In late '22, we have secured some funding from the NLnet Foundation alowing us to work on Verilog-AMS support. Within the next months, we will work on two tasks. One task is a compiler for behavioural models, the other is Verilog support on the simulator level.
Each task has 8 milestones. Here we will give details and keep track of our progress.
(See here for the follow-up.)
Branches and Contributions are explained here. The implementation is part of the develop branch as of March 5.
How to evaluate partial derivatives. An implementation is ready here. This Task is complete.
It's out and tagged 20230520-dev.
The code generation for while/for loops, case/ifthenelse/ternary is ready. Since 20230729-dev, the code generation for built-in functions, tasks and filters is based on FUNCTION plugins.
LRM and Designers guide contains copyrighted material. We have our own set of unit tests, growing as we progress. Type “make check”.
Verilog defines “paramset” as a means to replace model cards known from spice, cf. LRM section 6.4. The standard essentially allows multiple prototypes by the same name with mutually different interfaces (see usage), allowing things like recursive models. This requires changes to the way device instances are read in and elaborated. Preliminary code is available here. Some of it has been added to Gnucsator.
Slightly deviating from the workplan, we have added Preprocessing for compiler directives directly to the model compiler. The code is available here and combines preprocessing with evaluating derivatives (Task 1b).
Attributes are the little bits of info that are important in a different context, like schematics and PC boards. Verilog gives us a standard way to do this. It's now implemented in lang_verilog. It's in the snapshot, and in the “attributes-5” branch. here. There is technical documentation here and user documentation for its use in Verilog here.
This is working now. It's in the snapshot here and in the “logic-4” branch here. There is a first cut at user documentation here. This part (2d) is complete, but it will change as task 2e is done, and again when LRM compliant connectmodule insertion (planned for early 2024) is done.
To be able to use models implemented for Spice in a Verilog environment, we need to be able to reference these models from paramset statements. Spice has both component letters and model identifiers, whereas Verilog only uses type names etc.. Spice hardwires the segmentation into shared and individual storage, while Verilog leaves it to the user. We may have to find a way to avoid performance regressions.
Historically, the dc sweep command only sweeps element values, following other implementations such as Spice 1-3 and Ngspice. We have redefined the data path for parameter values in devices, in particular “precalc_last” and edited simple devices (elements) accordingly. With these changes, we provide parameter sweeps in Gnucsator, mirroring Qucsator behaviour. We have refactored and adjusted the default dc command plugin and added support for parameter sweeps. Many new tests have been added in the process. This task is completed and part of the 20230214 snapshot.
Currently, Gnucap loads precompiled binary plugins. We will automate the compilation process for a better user experience, especially because Verilog-AMS behavioural code must be compiled prior to loading.
Each continuous variable in the analog context carries a list of inputs (“probe”) it depends on. This is used to determine the model topology and to compute the partial derivatives accordingly. We also need to keep track of whether a derivative is constant. This task adds the required propagation rules and bookkeeping.
These are included with the 20231031 snapshot alongside constant folding.
Under the conditions identified in 3a, the evaluation and convergence checks in controlled sources can be unnecessary. For example, a constant resistor does not need re-evaluation, and is always converged by definition. In this task, these optimisations will be implemented for resistors and other linear devices.
This task is closed to finished with the November snapshot. Paramset has taken priority over this one.
A common pattern in compact modelling are “optional internal nodes”. In practice, the potential across two nodes can be set to zero. With 3a and 3b, this condition can be identified. In this task, the elaboration will be extended to avoid additional nodes.
Since November, the optional internal nodes (“V<+0.”) are collapsed into ports, and also nodes in ddt/idt filters are optimised out, where they are not needed.
Depending on instance parameters, contribution statements may be unreachable. Corresponding sources and model topology are bound to be more complex than needed. In this task the inferred source type will depend on the desired role, and unused sources will be optimised out. Constant folding from 1a predetermines reachability in conditional blocks.
Since 20231031 unreachable contributions are eliminated before any code is generated.