SPICE has irregular and confusing syntax. The preferred way to use SPICE models is through subckt declarations. A subckt declaration can be parsed while the language is set to spice. Case sensitivity can be enabled (default is off in spice), in order to avoid problems later, when the netlist is expanded.

spice
.options noinsensitive
.subcircuit mydev(a, b)
.parameter r=1
R1 a b r
.ends

The device above may contain more elaborate models and/or behavioural modeling quirks. Regardless it is now available, e.g. after switching to verilog (verilog is case sensitive by default).

verilog
mydev #(.r(1k)) my_resistor(p, 0);
vsource #(.v(1)) v1(p, 0);

// these commands are specific to gnucap
print dc v(p) i(my_resistor.R1)
dc